Device Physics for Computation

There are several research efforts into quantum devices on both the UCB Campus and at LBNL exploring device-level physics; our focus is in monitoring for future computational exploitation.  At the Berkeley Quantum Nanoelectronics Laboratory, Irfan Siddiqi and team are fabricating transmon qubit devices, and several ALS researchers and Materials Science members are also exploring superconducting and physical manifestations at the Lab such as trapped ion information processing.  

At the Lab's Ion Beam Technology Group, Thomas Schenkel and team are working to develop the theory, fabrication, and measurement aspects of a silicon-based ("Kane") approach to quantum computing. The monitored implantation, to nanometer accuracy, of a single ion has been achieved in the effort to implement a qubit array.

At the nearby UC Berkeley Quantum Architecture Research Center, John Kubiatowicz and team are exploring hardware organizations for expressing quantum circuits in useful architectures via a custom quantum CAD flow targeting Qalypso for ion trap computing.  This group also has an effort to utilize the CHISEL HW construction language supported the DOE and LBL to produce quantum-specific circuits.  


The CAL Lab funds and uses CHISEL for advanced architecture work on conventional architectures; presumably some of these insights will migrate to the quantum computing space to directly address HPC and DOE-specific needs.

In the commercial space, we also monitor emerging practical hardware which embodies advanced methods such as the D-Wave quantum computer.  Recently we received a full NDA technical debriefing of the characteristics and capabilities of the 1028 qubit system.
  
D-Wave’s quantum computer runs a quantum annealing algorithm to find the minima, corresponding to optimal or near optimal solutions, in a virtual “energy landscape.” Every additional qubit doubles the search space of the processor. At 1000 qubits, the new processor considers 2^1000 possibilities simultaneously theoretically exceeding the number of ‪particles in the observable universe.

By most accounts, future HPC platforms will incorporporate significant optical signaling.  The CAL Lab is monitoring three avenues at present: a direct-to-register fully integrated optical waveguide and conversion substrate delivering multi-Tbps to each core (undisclosed NDA partnership), an integrated monolithic transceiver test chip combined with the UC Berkeley RISC-V processor developed by Krste Asanovic and David Patterson, and ongoing collaborations with the Keren Bergman Lightwave Research Lab at Columbia University.




 Within the CAL Lab, we also are following various memory technologies as they evolve, and evaluating applicability to Exascale especially with respect to energy per bit.   Here is a comparison presentation from an internal seminar series for Exascale Memory Technology (also linked at bottom of this page).



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Aug 27, 2015, 3:06 PM
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